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[Compress-Decompress algrithmsPIE_encoder_model

Description: PIE(Pulse Interval Encoder) Simulink embedded model that i have made for my RFID Project
Platform: | Size: 8192 | Author: Adnan | Hits:

[Compress-Decompress algrithmsPIE_decoder_model

Description: PIE(pulse interval decoder)- Its the PIE decoder that I built for my RFID project. Its an ambedded simulink model.
Platform: | Size: 8192 | Author: Adnan | Hits:

[matlabRFIDtanslate

Description: 用Matlab仿真了基于EPC-C1G2标准的RFID阅读器发送模块的PIE编码及ASK调制。-Simulation using Matlab based on EPC-C1G2 standard RFID readers to send the module code and ASK modulation PIE.
Platform: | Size: 1024 | Author: 朵朵 | Hits:

[VHDL-FPGA-VerilogUHF-RFID-CRC

Description: 本文首先研究了IsO/IECl8000.6标准中A、B两类短程通讯的前向链路与返回 链路的数据编码方式,对(FMO)双相间隔编码、(PIE)脉冲间隔编码、曼切斯特码 的编解码方式和技术参数进行了深入的分析,并利用FPGA实验平台对这三种编 码的编、解码电路进行了设计和仿真。然后对UHF RFID系统的差错控制技术原理 进行了探讨,重点研究了ISo/IECl8000.6标准中采用的数据保护与校验技术,即 循环冗余校验(CRC)技术。分析了基于线性反馈移位寄存器(LFSR)实现CRC的电 路,从理论和实现两个方面对其中存在的问题提出了解决办法,设计了一种改进 型线性反馈移位寄存器电路来实现循环冗余校验。对于要求CRC运算速度高的系 统,本文利用了递归的算法设计了一种新型的并行CRC电路。最后本文提出了一 种新颖的UHF RFID系统数字基带电路,区别于一般数字基带电路的地方是:在编 解码模块和CRC模块之间加入了卷积编码和维特比译码模块。利用卷积码优良的 纠错能力,来解决UHF RFID系统在电磁干扰严重的环境中识别率低、通信速度慢 的问题,效果良好。-The first,this paper investigates the f.0rward link and retum link data encodlng method in short range communication types A and B in ISO/IEC 1 8000-6,and deeply analyzes encoding method and technical parameters of Bi—Phase Space(FMO)coding, Pulse IntervaI Encoding(PIE)coding and Manchester coding.We also designed and simulated code circuits and decode circuits of the three encoding method by FPGA experiment platfoml. The second, We discussed the technical principle of error control of the UHF RFID system,especially for the techn0109y of data Verification 肌d calibration,namely cyclic redundancy check that used in IS0/IEC 1 8000·6·The circuits of CRC based on Linear Feedback Shin Register(LSFR)are analyzed行om theonr and realization,and some means of solVing problems are put fon)Irard,then an improved LSFR circuit to implement CRC is designed.For some require fast CRC calculation system,we designed a noVel parallel CRC circuit by using recurslVe fomlula.In the end,we put forw
Platform: | Size: 4366336 | Author: HY jian | Hits:

[VHDL-FPGA-Verilogpie

Description: 自己设计的RFID中的PIE编码,如果有错误欢迎改正。希望能给大家带来帮助。-RFID in their own design PIE encoding, if the error correction welcome. Hope that we can bring help.
Platform: | Size: 1024 | Author: 成杰 | Hits:

[RFIDpie_decoder

Description: rfid电子标签数字基带处理中pie decoder-rfid electroic card digital signal processing of pie decoder
Platform: | Size: 1024 | Author: lvjian | Hits:

[VHDL-FPGA-VerilogPIE

Description: PIE DECDODER decotes pulse interval encoding dignal of RFID tags. OUTPUT is serial bits and parallel register (128 width).
Platform: | Size: 5120 | Author: harvanek | Hits:

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